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In STT-MRAM, when the technology moves towards smaller nodes, the switching current reduces faster than available transistor drive current, making it easier to scale down the STT-MRAM technology. The other important limitation consists of an issue known as “half-select.” The switching of a given cell is achieved by passing current through two orthogonal metallic lines: the bit line, which is above the storage cell, and the word line, which is below the storage cell (Figure 1). Thus, other cells, which are located below or above the current-carrying metallic lines also experience a magnetic field, which although smaller in magnitude may introduce inadvertent switching of these half-selected cells. This problem has been approached by introducing various special shapes for the MRAM element or by using synthetic antiferromagnetic (SAF) free layers. In STT-MRAM, the switching is achieved by passing current directly through magnetic layers in the selected cell, eliminating this problem entirely. In addition to the above-mentioned issues with conventional MRAM, the design of the STT-MRAM cell is much simpler: the bypass line and word line are eliminated. The smallest size for STTMRAM cell is 6F2 for in-plane design, 4F2 for perpendicular design and even smaller for multiple-level cell (MLC) design, which employs two or more storage elements per single nanopillar.(ACM Journal on Emerging Technologies in Computing Systems, Vol. 9, No. 2, Article 13, Pub. date: May 2013.)

The demonstration that MRAM cells could be written by spin transfer torque (STT) from spin-polarized electrical current10,11 instead of a magnetic field rekindled the interest in MRAM technology.12–15 Indeed, contrary to Field MRAMs, the same bit lines can be used to read and write STT-MRAM cells by simply driving current directly through the cell (Fig. 1(b)). This allows for much simpler design, denser layout, improved scalability, and power consumption. The latest development of in-plane STT- MRAMs was reported recently by Everspin Technolo gies, which has demonstrated a fully functional 64 Mb STT-MRAM chip.(JOURNAL OF APPLIED PHYSICS 115, 172615 (2014))